1. Technical Field
The present invention relates to a test apparatus. More particularly, the present invention relates to a test apparatus for testing a device under test such as a semiconductor chip.
2. Related Art
When a device under test such as a semiconductor chip is tested, the test may be performed to measure the amount of jitter contained in an output signal from the device under test. The jitter represents, for example, a difference in time between the edge timing of an ideal signal and the edge timing of an actual signal. Therefore, the jitter can be measured by measuring the edge timing of the actual signal.
For example, the logical value of the output signal is sampled at a predetermined sampling interval, and the samples are stored on a memory. The data on the memory is analyzed so as to detect the logical transition timing of the output signal. Here, a difference in time between the timing of each transition and the timing of a corresponding ideal transition is acquired. In this way, the timing jitter of the output signal can be obtained (for example, see Unexamined Japanese Patent Application Publication No. 2004-125552).
Here, the measured jitter is equivalent to accumulation of various types of jitter caused by many different factors. The jitter is generated by a variety of factors including, for example, power source noise in the device under test, clock noise, noise in each circuit block, and measurement noise. Here, the conventional jitter measuring technique has difficulties in analyzing the measurement result stored on the memory to identify factors that cause a particular type of jitter.